The subject matter disclosed herein relates to methods and test structures for integrated circuits (ICs). More specifically, aspects of the invention relate to test and monitoring structures which can measure the reliability of an IC chip and its components, e.g., metal level layers and interlayer dielectrics therein.
Each IC of a particular device can be made up of billions of interconnected devices, such as transistors, resistors, capacitors, and diodes, located on one or more chips of semiconductor substrate material. The quality and viability of a product including an IC can be at least partially dependent on the techniques used for fabricating the IC and the structure of various components therein. Fabrication of an IC can include two phases: front-end-of-line processes (FEOL) and back-end-of-line processes (BEOL). FEOL generally includes fabrication processes performed on a wafer up to and including the formation of a first “metal level,” i.e., a metal wire for connecting several semiconductor devices together. BEOL generally includes fabrication processes following the formation of the first metal level, including the formation of all subsequent metal levels. To provide greater scaling and sophistication of the fabricated device, the number of metal levels can be varied to suit a particular application, e.g., by providing four to six metal levels, or as many as, in a further example, sixteen or more metal levels.
Two or more metal levels can be electrically interconnected by the use of vertical metal wires, also known as “vias.” Each via can traverse one or more regions of interlayer dielectric material, in addition to other intervening metal levels. Vias can present a significant manufacturing challenge, because a single broken contact or electrical short can affect the operation of an entire product. As a result, accurate prediction or signaling of chip-level failure rate can be especially significant where, e.g., interlayer dielectrics are particularly thin and where a large number of vias are included. Conventional test structures can include long, intertwined conductive chains of metal wires. These types of test structures may be highly resistive and cause overestimations of failure rate because of the test current and “leakage” currents being of similar magnitude. Alternative test structures may be more sensitive to changes in current, but may not test for a worst-case scenario due to differences in their underlying structure.